Quick data recovery from corrupted (truncated) python pickle files.
FTDI's FT60X USB 3 bridge chips are infamous for a slightly tricky interface. We take a look at how to derive correct timing constraints for a custom board and implement an interface capable of the full bandwidth, even on a low-end FPGA.
How to hook up a 60€ USB oscilloscope as a (baseband / IF) sample source to GNU Radio and build a simple FM receiver
An overview of common cheap clock generators, PLLs and DDS modules from AliExpress, eBay, etc. which can be useful as local oscillators for prototyping
